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1 note: for ATV2500Bq and ATV2500Bql (plcc/lcc package only) pin 4 and pin 26 connections are not required. pin configurations pin name function in logic inputs clk/in pin clock and input i/o bi-directional buffers i/o 0,2,4.. ?even? i/o buffers i/o 1,3,5.. ?odd? i/o buffers gnd ground vcc +5v supply features high-performance, high-density programmable logic device ? typical 7 ns pin-to-pin delay ? fully connected logic array with 416 product terms flexible output macrocell ? 48 flip-flops ? two per macrocell ?72 sum terms ? all flip-flops, i/o pins feed in independently ? achieves over 80% gate utilization enhanced macrocell configuration selections ? d- or t-type flip-flops ? product term or direct input pin clocking ? registered or combinatorial internal feedback several power saving options backward compatible with atv2500h/l software proven and reliable high-speed uv eprom process reprogrammable ? tested 100% for programmability 40-lead dual-in-line and 44-lead surface mount packages block diagram device i cc , standby ATV2500B 110 ma ATV2500Bq 30 ma ATV2500Bl 2 ma ATV2500Bql 2 ma rev. 0249j?05/00 high-speed high-density uv-erasable programmable logic device ATV2500B ATV2500Bq ATV2500Bql lcc/plcc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 i/o2 i/o3 i/o4 i/o5 vcc vcc i/o17 i/o16 i/o15 i/o14 i/o13 i/o7 i/o8 i/o9 i/o10 i/o11 gnd gnd i/o23 i/o22 i/o21 i/o20 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 i/o12 in in in in in in in gnd i/o18 i/o19 i/o1 i/o0 gnd in in clk/in in in in in i/o06 dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 clk/in in in i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 vcc i/o17 i/o16 i/o15 i/o14 i/o13 i/o12 in in in in in in in in i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 gnd i/o23 i/o22 i/o21 i/o20 i/o19 i/o18 in in in
ATV2500B(q)(l) 2 functional logic diagram ATV2500B note: 1. not required for plcc versions of ATV2500Bq or ATV2500Bql, making them compatible with atv2500h and atv2500l pinout.
ATV2500B(q)(l) 3 description the ATV2500Bs are the highest density plds available in a 40- or 44-lead package. with their fully connected logic array and flexible macrocell structure, high-gate utilization is easily obtainable. the ATV2500Bs are organized around a single universal and-or array. all pins and feedback terms are always avail- able to every macrocell. each of the 38 logic pins are array inputs, as are the outputs of each flip-flop. in the ATV2500Bs, four product terms are input to each sum term. furthermore, each macrocell ? s three sum terms can be combined to provide up to 12 product terms per sum term with no performance penalty. each flip-flop is individually selectable to be either d- or t-type, providing further logic compaction. also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array. product terms provide individual clocks and asynchronous resets for each flip-flop. the flip-flops may also be individu- ally configured to have direct input pin clocking. each output has its own enable product term. eight synchronous preset product terms serve local groups of either four or eight flip-flops. register preload functions are provided to simplify testing. all registers automatically reset upon power-up. several low-power device options allow selection of the optimum solution for many power-sensitive applications. each of the options significantly reduces total system power and enhances system reliability. functional logic diagram description the ATV2500B functional logic diagram describes the interconnections between the input, feedback pins and logic cells. all interconnections are routed through the single global bus. the ATV2500Bs are straightforward and uniform plds. the 24 macrocells are numbered 0 through 23. each mac- rocell contains 17 and gates. all and gates have 172 inputs. the five lower product terms provide ar1, ck1, ck2, ar2, and oe. these are: one asynchronous reset and clock per flip-flop, and an output enable. the top 12 product terms are grouped into three sum terms, which are used as shown in the macrocell diagrams. eight synchronous preset terms are distributed in a 2/4 pat- tern. the first four macrocells share preset 0, the next two share preset 1, and so on, ending with the last two macro- cells sharing preset 7. the 14 dedicated inputs and their complements use the numbered positions in the global bus as shown. each mac- rocell provides six inputs to the global bus: (left to right) feedback f2 (1) true and false, flip-flop q1 true and false, and the pin true and false. the positions occupied by these signals in the global bus are the six numbers in the bus dia- gram next to each macrocell. note: 1. either the flip-flop input (d/t2) or output (q2) may be
ATV2500B(q)(l) 4 note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. absolute maximum ratings* temperature under bias................................ -55 c to +125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc which may under- shoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc + 0.75v dc which may overshoot to +7.0v for pulses of less than 20 ns. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) integrated uv erase dose..............................7258 w sec/cm 2 dc and ac operating conditions commercial industrial military operating temperature 0 c - 70 c (ambient) -40 c - 85 c (ambient) -55 c - 125 c (case) v cc power supply 5v 5% 5v 10% 5v 10% pin capacitance f = 1 mhz, t = 25 c (1) typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
ATV2500B(q)(l) 5 output logic, registered (1) output logic, combinatiorial (1) note: 1. these diagrams show equivalent logic functions, not necessarily the actual circuit implementation. note: 1. these four terms are shared with d/t1. clock option s2 = 0 terms in output configuration s1 s0 d/t1 d/t2 0084registered (q1); q2 fb 10124 (1) registered (q1); q2 fb 1184registered (q1); d/t2 fb s3 output configuration s6 q1 clock 0 active low 0 ck1 1 active high 1 ck1 pin1 s4 register 1 type s7 q2 clock 0d 0ck2 1t 1ck2 pin1 s5 register 2 type 0d 1t s2 = 1 terms in output configuration s5 s1 s0 d/t1 d/t2 x004 (1) 4 combinatorial (8 terms); q2 fb x0144 combinatorial (4 terms); q2 fb x104 (1) 4 (1) combinatorial (12 terms); q2 fb 1114 (1) 4 combinatorial (8 terms); d/t2 fb 01144 combinatorial (4 terms); d/t2 fb
ATV2500B(q)(l) 6 note: 1. see i cc versus frequency characterization curves. dc characteristics symbol parameter condition min typ max units i il input load current v in = -0.1v to v cc + 1v 10 a i lo output leakage current v out = -0.1v to v cc + 0.1v 10 a i cc power supply current, standby v cc = max, v in = gnd or v cc f = 0 mhz, outputs open ATV2500B com. 110 190 ma ind., mil. 110 210 ma ATV2500Bq com. 30 70 ma ind., mil. 30 85 ma ATV2500Bl com. 2 5 ma ind., mil. 2 10 ma ATV2500Bql com. 2 4 ma ind., mil. 2 5 ma i os output short circuit current v out = 0.5v -120 ma v il input low voltage min v cc max -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.75 v v ol output low voltage v in = v ih or v il , v cc = 4.5v i ol = 8 ma com., ind. 0.5 v i ol = 6 ma mil. 0.5 v v oh output high voltage v cc = min i oh = -100 a v cc - 0.3 v i oh = -4.0 ma 2.4
ATV2500B(q)(l) 7 ac waveforms (1) input pin clock ac waveforms (1) product term clock note: 1. timing measurement reference is 1.5v. input ac driving levels are 0.0v and 3.0v, unless otherwise specified.
ATV2500B(q)(l) 8 register ac characteristics, input pin clock symbol parameter -12 -15 -20 -25 -30 units min max min max min max min max min max t cos clock to output 7.510111215ns t cfs clock to feedback 0405060708 ns t sis input setup time 7 9 14 20 23 ns t sfs feedback setup time 7 9 14 20 23 ns t hs hold time 00000 ns t ws clock width 56789 ns t ps clock period 10 12 14 16 18 ns f maxs external feedback 1/(t sis + t cos )6952403126mhz internal feedback 1/(t sfs + t cfs )9071503732mhz no feedback 1/(t ps ) 100 83 71 62 55 mhz t ars asynchronous reset/preset recovery time 7 12152025 ns
ATV2500B(q)(l) 9 ac waveforms (1) combinatorial outputs and feedback note: 1. timing measurement reference is 1.5v. input ac driving levels are 0.0v and 3.0v, unless otherwise specified. register ac characteristics, product term clock symbol parameter -12 -15 -20 -25 -30 units min max min max min max min max min max t coa clock to output 12 15 20 22 25 ns t cfa clock to feedback 3 7 5 12 10 16 12 18 13 20 ns t sia input setup time 4 5 10 15 19 ns t sfa feedback setup time 4 5 8 10 10 ns t ha hold time 3 5 10 12 13 ns t wa clock width 5.5 7.5 11 14 15 ns t pa clock period 11 15 22 28 30 ns f maxa external feedback 1/(t sia + t coa )62.550332723mhz internal feedback 1/(t sfa + t cfa ) 9058383624mhz no feedback 1/(t ps ) 9066453633mhz t ara asynchronous reset/preset recovery time 3 8 12 15 18 ns
ATV2500B(q)(l) 10 input test waveforms and measurement levels output test load preload and observability of registered outputs the ATV2500Bs registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. this feature will simplify testing since any state can be forced into the registers to control test sequencing. a v ih level on the odd i/o pins will force the appropriate register high; a v il will force it low, independent of the polarity or other configuration bit settings. the preload state is entered by placing an 10.25v to 10.75v signal on smp lead 42. when the preload clock smp lead 23 is pulsed high, the data on the i/o pins is placed into the 12 registers chosen by the q select and even/odd select pins. register 2 observability mode is entered by placing an 10.25v to 10.75v signal on pin/lead 2. in this mode, the contents of the buried register bank will appear on the associated outputs when the oe control signals are active. ac characteristics symbol parameter -12 -15 -20 -25 -30 units min max min max min max min max min max t pd1 input to non-registered output 12 15 20 25 30 ns t pd2 feedback to non-registered output 12 15 20 25 30 ns t pd3 input to non-registered feedback 8 11 15 18 20 ns t pd4 feedback to non-registered feedback 811151820ns t ea1 input to output enable 12 15 20 25 30 ns t er1 input to output disable 12 15 20 25 30 ns t ea2 feedback to output enable 12 15 20 25 30 ns t er2 feedback to output disable 12 15 20 25 30 ns t aw asynchronous reset width 6 8 12 15 18 ns t ap asynchronous reset to registered output 15 18 22 28 30 ns t apf asynchronous reset to registered feedback 12 15 19 25 30 ns
ATV2500B(q)(l) 11 power-up reset the registers in the ATV2500Bs are designed to reset dur- ing power-up. at a point delayed slightly from v cc crossing v rst , all registers will be reset to the low state. the output state will depend on the polarity of the output buffer. this feature is critical for state as nature of reset and the uncertainty of how v cc actually rises in the system, the fol- lowing conditions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock pin or terms high, and 3. the clock pin, and any signals from which clock terms are derived, must remain stable during t pr . . level forced on odd i/o pin during preload cycle q select pin state even/odd select even q1 state after cycle even q2 state after cycle odd q1 state after cycle odd q2 state after cycle v ih /v il low low high/low x x x v ih /v il high low x high/low x x v ih /v il low high x x high/low x v ih /v il high high x x x high/low parameter description typ max units t pr power-up reset time 600 1000 ns v rst power-up reset voltage 3.8 4.5 v
ATV2500B(q)(l) 12 security fuse usage a single fuse is provided to prevent unauthorized copying of ATV2500B fuse patterns. once programmed, the out- puts will read programmed during verify. the security fuse should be programmed last, as its effect is immediate. the security fuse also inhibits preload and q2 observability. atmel cmos plds the ATV2500Bs utilize an advanced 0.65-micron cmos eprom technology. this technology ? s state of the art fea- tures are the optimum combination for plds: cmos technology provides high speed, low power, and high noise immunity. eprom technology is the most cost effective method for producing plds ? surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability. eprom reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible plds. using the ATV2500Bs many advanced features the ATV2500Bs advanced flexibility packs more usable gates into 44 leads than other plds. some of the ATV2500Bs key features are: fully connected logic array ? each array input is always available to every product term. this makes logic placement a breeze. selectable d- and t-type registers ? each ATV2500B flip-flop can be individually configured as either d- or t- type. using the t-type configuration, jk and sr flip-flops are also easily created. these options allow more efficient product term usage. buried combinatorial feedback ? each macrocell ? s q2 register may be bypassed to feed its input (d/t2) directly back to the logic array. this provides further logic expansion capability without using precious pin resources. selectable synchronous/asynchronous clocking ? each of the ATV2500Bs flip-flops has a dedicated clock product term. this removes the constraint that all registers use the same clock. buried state machines, counters and registers can all coexist in one device while running on separate clocks. individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. a total of 48 registers ? the ATV2500B provides two flip-flops per macrocell ? a total of 48. each register has its own clock and reset terms, as well as its own sum term. independent i/o pin and feedback paths ? each i/o pin on the ATV2500B has a dedicated input path. each of the 48 registers has its own feedback term into the array as well. these features, combined with individual product terms for each i/o ? s output enable, facilitate true bi-directional i/o design. combinable sum terms ? each output macrocell ? s three sum terms may be combined into a single term. this provides a fan in of up to 12 product terms per sum term with no speed penalty. programming software support as with all other atmel plds, several third party pld devel- opment software products and programmers will support the ATV2500Bs. several third party programmers will support the ATV2500B as well. additionally, the ATV2500B may be programmed to perform the atv2500h/ls functional sub- set (no t-type flip-flops, pin clocking or d/t2 feedback) using the atv2500h/l jedec file. in this case, the ATV2500B becomes a direct replacement or speed upgrade for the atv2500h/l (additional gnd connections are required). please refer to the programmable logic development tools section for a complete pld software and programmer listing. erasure characteristics the entire memory array of an ATV2500B is erased after exposure to ultraviolet light at a wavelength of 2537 ? . complete erasure is assured after a minimum of 20 min- utes exposure using 12,000 w/cm 2 intensity lamps spaced one inch away from the chip. minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 w sec/cm 2 . to prevent unintentional erasure, an opaque label is recom- mended to cover the clear window on any uv erasable pld which will be subjected to continuous fluorescent indoor lighting or sunlight.
ATV2500B(q)(l) 13 note: 1. all normalized values referenced to maximum specification in ac characteristics of data sheet.
ATV2500B(q)(l) 14 output source current vs. output volt age (vcc=5v,ta=25 c) -5 -4 -3 -2 -1 0 3.5 3.8 4.1 4.4 4.7 5.0 output volt age (v) i o h m a output source current vs. output volt age (vcc=5v,ta=25 c) -80 -60 -40 -20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5. 0 output volt age (v) i o h m a normalized tco vs. supply voltage (ta=25 c) 0.8 0.9 1.0 1.1 1.2 1.3 4.50 4.75 5.00 5.25 5.50 supply voltage (v) n o r m t c o ATV2500Bq(l) ATV2500B(l) normalized tpd vs. ambient temperature (vcc = 5v) 0.8 0.9 1.0 1.1 1.2 1.3 -55-255 35659512 5 ambient temperature (c) n o r m t p d ATV2500B(l) ATV2500Bq(l) normalized tco vs. ambient temperature (vcc = 5v) 0.8 0.9 1.0 1.1 1.2 1.3 -55 -25 5 35 65 95 12 5 ambient temperature (c) n o r m t c o ATV2500B(l) ATV2500Bq(l) note: 1. all normalized values referenced to maximum specification in ac characteristics of data sheet.
ATV2500B(q)(l) 15 note: 1. all normalized values referenced to maximum specification in ac characteristics of data sheet.
ATV2500B(q)(l) 16 ordering information t pd (ns) t cos (ns) ext. f maxs (mhz) ordering code package operation range 12 7.5 69 ATV2500B-12jc ATV2500B-12kc 44j 44kw commercial (0 c to 70 c) 15 10 52 ATV2500B-15jc ATV2500B-15kc 44j 44kw commercial (0 c to 70 c) ATV2500B-15ji ATV2500B-15ki 44j 44kw industrial (-40 c to 85 c) ATV2500B-15km ATV2500B-15lm 44kw 44lw military (-55 c to 125 c) ATV2500B-15km/883 ATV2500B-15lm/883 44kw 44lw military/883c (-55 c to 125 c) class b, fully compliant 20 11 40 ATV2500Bl-20jc ATV2500Bl-20kc 44j 44kw commercial (0 c to 70 c) ATV2500Bl-20ji ATV2500Bl-20ki 44j 44kw industrial (-40 c to 85 c) ATV2500Bl-20km ATV2500Bl-20lm 44kw 44lw military (-55 c to 125 c) ATV2500Bl-20km/883 ATV2500Bl-20lm/883 44kw 44lw military/883c (-55 c to 125 c) class b, fully compliant 20 11 40 ATV2500Bq-20dc ATV2500Bq-20jc ATV2500Bq-20kc ATV2500Bq-20pc 40dw6 44j 44kw 40p6 commercial (0 c to 70 c) using ? c ? product for industrial to use commercial product for industrial temperature ranges, down-grade one speed grade from the ? i ? to the ? c ? device (7 ns ? c ? = 10 ns ? i ? ) and de-rate power by 30%. package type 40dw6 40-pin, 0.600" wide, ceramic, dual inline package (cerdip) 44j 44-lead, plastic j-leaded chip carrier otp (plcc) 44kw 44-lead, windowed, ceramic j-leaded chip carrier (jlcc) 40p6 40-pin, 0.600" wide, plastic, dual inline package otp (pdip) 44lw 44-pad, windowed, ceramic leadless chip carrier (lcc)
ATV2500B(q)(l) 17 25 12 31 ATV2500Bq-25dc ATV2500Bq-25jc ATV2500Bq-25kc ATV2500Bq-25pc 40dw6 44j 44kw 40p6 commercial (0 c to 70 c) ATV2500Bq-25di ATV2500Bq-25ji ATV2500Bq-25ki ATV2500Bq-25pi 40dw6 44j 44kw 40p6 industrial (-40 c to 85 c) ATV2500Bq-25dm ATV2500Bq-25km ATV2500Bq-25lm 40dw6 44kw 44lw military/883c (-55 c to 125 c) ATV2500Bq-25dm/883 ATV2500Bq-25km/883 ATV2500Bq-25lm/883 40dw6 44kw 44lw military/883c (-55 c to 125 c) class b, fully compliant 25 12 31 ATV2500Bql-25dc ATV2500Bql-25jc ATV2500Bql-25kc ATV2500Bql-25pc 40dw6 44j 44kw 40p6 commercial (0 c to 70 c) 25 12 31 ATV2500Bql-25di ATV2500Bql-25ji ATV2500Bql-25ki ATV2500Bql-25pi 40dw6 44j 44kw 40p6 industrial (-40 c to 85 c) 30 15 26 ATV2500Bql-30dm ATV2500Bql-30km ATV2500Bql-30lm 40dw6 44kw 44lw military/883c (-55 c to 125 c) 15 26 ATV2500Bql-30dm/883 ATV2500Bql-30km/883 ATV2500Bql-30lm/883 40dw6 44kw 44lw military/883c (-55 c to 125 c) class b, fully compliant ordering information (continued) t pd (ns) t cos (ns) ext. f maxs (mhz) ordering code package operation range using ? c ? product for industrial to use commercial product for industrial temperature ranges, down-grade one speed grade from the ? i ? to the ? c ? device (7 ns ? c ? = 10 ns ? i ? ) and de-rate power by 30%. package type 40dw6 40-pin, 0.600" wide, ceramic, dual inline package (cerdip) 44j 44-lead, plastic j-leaded chip carrier otp (plcc) 44kw 44-lead, windowed, ceramic j-leaded chip carrier (jlcc) 40p6 40-pin, 0.600" wide, plastic, dual inline package otp (pdip) 44lw 44-pad, windowed, ceramic leadless chip carrier (lcc)
ATV2500B(q)(l) 18 using ? c ? product for industrial to use commercial product for industrial temperature ranges, down-grade one speed grade from the ? i ? to the ? c ? device (7 ns ? c ? = 10 ns ? i ? ) and de-rate power by 30%. 15 10 52 5962 - 9154504mxx 5962 - 9154504myx 44lw 44kw military/883c (-55 c to 125 c) class b, fully compliant 20 11 40 5962 - 9154505mxx 5962 - 9154505myx 44lw 44kw military/883c (-55 c to 125 c) class b, fully compliant 25 12 31 5962 - 9154506mxx 5962 - 9154506myx 5962 - 9154506mqa 44lw 44kw 40dw6 military/883c (-55 c to 125 c) class b, fully compliant 30 15 26 5962 - 9154507mxx 5962 - 9154507myx 5962 - 9154507mqa 44lw 44kw 40dw6 military/883c (-55 c to 125 c) class b, fully compliant package type 40dw6 40-pin, 0.600" wide, ceramic, dual inline package (cerdip) 44j 44-lead, plastic j-leaded chip carrier otp (plcc) 44kw 44-lead, windowed, ceramic j-leaded chip carrier (jlcc) 40p6 40-pin, 0.600" wide, plastic, dual inline package otp (pdip) 44lw 44-pad, windowed, ceramic leadless chip carrier (lcc) ordering information (continued) t pd (ns) t cos (ns) ext. f maxs (mhz) ordering code package operation range
ATV2500B(q)(l) 19 packaging information .045(1.14) x 45 pin no. 1 identify .045(1.14) x 30 - 45 .012(.305) .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) ref sq .032(.813) .026(.660) .050(1.27) typ .022(.559) x 45 max (3x) .656(16.7) .650(16.5) .695(17.7) .685(17.4) sq sq .045(1.14) x 45 .032(.813) .026(.660) .050(1.27) typ .500(12.7) ref sq .035(.889) x 45 .010(.254) .006(.152) .021(.533) .017(.432) .630(16.0) .590(15.0) .045(1.14) .035(.889) .120(3.05) .090(2.29) .180(4.57) .156(3.96) .665(16.9) .645(16.4) .695(17.7) .685(17.4) sq sq .025(.635) radius max (3x) 2.07(52.6) 2.04(51.8) pin 1 .566(14.4) .530(13.5) .090(2.29) max .005(.127) min .065(1.65) .015(.381) .022(.559) .014(.356) .065(1.65) .041(1.04) 0 15 ref .690(17.5) .610(15.5) .630(16.0) .590(15.0) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) seating plane .220(5.59) max 1.900(48.26) ref 40dw6 , 40-pin, 0.600 ? wide, windowed, ceramic dual inline package (cerdip) dimensions in inches and (millimeters) mil-std-1835 d-5 config a 44j , 44-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 ac 44kw , 44-lead, windowed, ceramic j-leaded chip carrier (jlcc) dimensions in inches and (millimeters) mil-std-1835 cj1 40p6 , 40-pin, 0.600 ? wide, plastic dual inline package (pdip) dimensions in inches and (millimeters) jeded standard ms-011 ac
ATV2500B(q)(l) 20 packaging information *controlling dimension: millimeters 44lw , 44-pad, windowed, ceramic leadless chip carrier (lcc) dimensions in inches and (millimeters)* mil-std-1835 c-5
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